module top;
integer ia;
reg a;
wire out;
not_behavioral and1(out,a);
initial
begin
for (ia=0; ia<=1; ia = ia+1)
begin
a = ia;
#50 $display("a=%d out=%d",a,out);
end
end
endmodule
module not
_behavioral(out,a);
input a;
output out;
wire a;
reg out;
always @(a )
out = ~a ;
endmodule
end
endmodule
module not
_behavioral(out,a);
input a;
output out;
wire a;
reg out;
always @(a )
out = ~a ;
endmodule
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